receive_q1_ptr (GEM) Register Description
| Register Name | receive_q1_ptr |
|---|---|
| Offset Address | 0x0000000480 |
| Absolute Address |
0x00FF0B0480 (GEM0) 0x00FF0C0480 (GEM1) 0x00FF0D0480 (GEM2) 0x00FF0E0480 (GEM3) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of the system bus operation, the receive descriptors must be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64-bit bus access. |
receive_q1_ptr (GEM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| dma_rx_q_ptr | 31:2 | rwNormal read/write | 0x0 | Receive buffer queue base address - written with the address of the start of the receive queue. |
| Reserved | 1:0 | roRead-only | 0x0 | Reserved, read as 0, ignored on write. |