receive_status (GEM) Register Description
Register Name | receive_status |
---|---|
Offset Address | 0x0000000020 |
Absolute Address |
0x00FF0B0020 (GEM0) 0x00FF0C0020 (GEM1) 0x00FF0D0020 (GEM2) 0x00FF0E0020 (GEM3) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | This register, when read provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register. |
receive_status (GEM) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:4 | roRead-only | 0x0 | Reserved, read as 0, ignored on write. |
resp_not_ok | 3 | rwNormal read/write | 0x0 | bresp/hresp not OK - set when the DMA block sees bresp/hresp not OK. Cleared by writing a one to this bit. |
receive_overrun | 2 | rwNormal read/write | 0x0 | Receive overrun - this bit is set if either the gem_dma RX FIFO or external RX FIFO were unable to store the receive frame due to a FIFO overflow, or if the receive status, reported by the gem_rx module to the gem_dma was not taken at end of frame. This bit is also set in DMA packet buffer mode if the packet buffer overflows. For DMA operation the buffer will be recovered if an overrun occurs. This bit is cleared by writing a one to it. |
frame_received | 1 | rwNormal read/write | 0x0 | Frame received - one or more frames have been received and placed in memory. Cleared by writing a one to this bit. |
buffer_not_available | 0 | rwNormal read/write | 0x0 | Buffer not available - an attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA will reread the pointer each time an end of frame is received until a valid pointer is found. This bit is set following each descriptor read attempt that fails, even if consecutive pointers are unsuccessful and software has in the mean time cleared the status flag. Cleared by writing a one to this bit. |