rx_overruns (GEM) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

rx_overruns (GEM) Register Description

Register Namerx_overruns
Offset Address0x00000001A4
Absolute Address 0x00FF0B01A4 (GEM0)
0x00FF0C01A4 (GEM1)
0x00FF0D01A4 (GEM2)
0x00FF0E01A4 (GEM3)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionReceive Overruns

rx_overruns (GEM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:10roRead-only0x0Reserved, read as 0, ignored on write.
count 9:0rwNormal read/write0x0Receive overruns - a 10 bit register counting the number of frames that are address recognized but were not copied to memory due to a receive overrun.