slcr_gic (FPD_SLCR_SECURE) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

slcr_gic (FPD_SLCR_SECURE) Register Description

Register Nameslcr_gic
Offset Address0x0000000060
Absolute Address 0x00FD690060 (FPD_SLCR_SECURE)
Width 1
TyperwNormal read/write
Reset Value0x00000000
DescriptionAPU GIC setting.

Disable write access to certain Secure APU GIC control registers.

slcr_gic (FPD_SLCR_SECURE) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
cfg_disable 0rwNormal read/write0x0Disable write access to certain Secure registers of GIC.
It controls the GIC-400 CFGSDISABLE pin.
For details, please consult ARM GIC400_Technical_Reference Manual (DDI 0471B and up).