spec_add3_bottom (GEM) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

spec_add3_bottom (GEM) Register Description

Register Namespec_add3_bottom
Offset Address0x0000000098
Absolute Address 0x00FF0B0098 (GEM0)
0x00FF0C0098 (GEM1)
0x00FF0D0098 (GEM2)
0x00FF0E0098 (GEM3)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionThe addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written.

spec_add3_bottom (GEM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
address31:0rwNormal read/write0x0Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.