spec_add4_top (GEM) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

spec_add4_top (GEM) Register Description

Register Namespec_add4_top
Offset Address0x00000000A4
Absolute Address 0x00FF0B00A4 (GEM0)
0x00FF0C00A4 (GEM1)
0x00FF0D00A4 (GEM2)
0x00FF0E00A4 (GEM3)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionSpecific Address Top

spec_add4_top (GEM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:30roRead-only0x0Reserved, read as 0, ignored on write.
filter_byte_mask29:24rwNormal read/write0x0When high, the associated byte of the specific address will not be compared. Bit 24 controls whether the first byte received should be compared. Bit 29 controls whether the last byte received should be compared.
Reserved23:17roRead-only0x0Reserved, read as 0, ignored on write.
filter_type16rwNormal read/write0x0This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero, the filter is a destination address filter. When set to one, the filter is a source address filter. Specific address 1. The most significant bits of the destination address, that is bits 47:32.
address15:0rwNormal read/write0x0Specific address 1. The most significant bits of the destination/source address that is to be compared, that is bits 47:32.