transmit_q_ptr (GEM) Register Description
| Register Name | transmit_q_ptr |
|---|---|
| Offset Address | 0x000000001C |
| Absolute Address |
0x00FF0B001C (GEM0) 0x00FF0C001C (GEM1) 0x00FF0D001C (GEM2) 0x00FF0E001C (GEM3) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Since the DMA handles two frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of system bus operation, the transmit descriptors must be aligned at 64-bit boundaries for each pair of 32-bit descriptors. |
transmit_q_ptr (GEM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| dma_tx_q_ptr | 31:2 | rwNormal read/write | 0x0 | Transmit buffer queue base address - written with the address of the start of the transmit queue. |
| Reserved | 1:0 | roRead-only | 0x0 | Reserved, read as 0, ignored on write. |