transmit_status (GEM) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

transmit_status (GEM) Register Description

Register Nametransmit_status
Offset Address0x0000000014
Absolute Address 0x00FF0B0014 (GEM0)
0x00FF0C0014 (GEM1)
0x00FF0D0014 (GEM2)
0x00FF0E0014 (GEM3)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionThis register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.

transmit_status (GEM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:9roRead-only0x0Reserved, read as zero, ignored on write.
resp_not_ok 8rwNormal read/write0x0bresp/hresp not OK - set when the DMA block sees bresp/hresp not OK. Cleared by writing a one to this bit.
late_collision_occurred 7rwNormal read/write0x0Late collision occurred - only set if the condition occurs in gigabit mode, as retry is not attempted. Cleared by writing a one to this bit.
transmit_under_run 6rwNormal read/write0x0Transmit under run - this bit is set if the transmitter was forced to terminate a frame that it had already began transmitting due to further data being unavailable. This bit is set if a transmitter status write back has not completed when another status write back is attempted. When using the DMA interface configured for internal FIFO mode, this bit is also set when the transmit DMA has written the SOP data into the FIFO and either the AHB bus was not granted in time for further data, or because an AHB not OK response was returned, or because a used bit was read. When using the DMA interface configured for packet buffer mode, this bit will never be set. When using the external FIFO interface, this bit is also set when the tx_r_underflow input is asserted during a frame transfer. Cleared by writing a 1.
transmit_complete 5rwNormal read/write0x0Transmit complete - set when a frame has been transmitted. Cleared by writing a one to this bit.
amba_error 4rwNormal read/write0x0Transmit frame corruption due to AMBA (AHB/AXI) errors. Set if an error occurs whilst midway through reading transmit frame from external memory including HRESP(AHB), RRESP or BRESP(AXI) errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and tx_er asserted). Also set in DMA packet buffer mode if single frame is too large for configured packet buffer memory size. Cleared by writing a one to this bit.
transmit_go 3roRead-only0x0Transmit go - if high transmit is active. When using the exposed FIFO interface, this bit represents bit 3 of the network control register. When using the DMA interface this bit represents the tx_go variable as specified in the transmit buffer description.
retry_limit_exceeded 2rwNormal read/write0x0Retry limit exceeded - cleared by writing a one to this bit.
collision_occurred 1rwNormal read/write0x0Collision occurred - set by the assertion of collision. Cleared by writing a one to this bit. When operating in 10/100 mode, this status indicates either a collision or a late collision. In gigabit mode, this status is not set for a late collision.
used_bit_read 0rwNormal read/write0x0Used bit read - set when a transmit buffer descriptor is read with its used bit set. Cleared by writing a one to this bit.