tsu_h_cs (EFUSE) Register Description
| Register Name | tsu_h_cs |
|---|---|
| Offset Address | 0x000000002C |
| Absolute Address | 0x00FFCC002C (EFUSE) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000007 |
| Description | CS to STROBE timing |
tsu_h_cs (EFUSE) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| value | 3:0 | rwNormal read/write | 0x7 | Count value for the CSB/LOAD/PGENB to STROBE setup/hold timing parameter. The default value is set for a 220MHz clock. This value can be reconfigured using the following equation: ceiling(30ns / efuse_clk period) where efuse_clk is selected by the CFG register. |