tsu_h_ps_cs (EFUSE) Register Description
| Register Name | tsu_h_ps_cs |
|---|---|
| Offset Address | 0x0000000024 |
| Absolute Address | 0x00FFCC0024 (EFUSE) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x0000000B |
| Description | PS to CS timing |
tsu_h_ps_cs (EFUSE) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| value | 7:0 | rwNormal read/write | 0xB | Count value for the PS to CSB setup/hold timing paramter. The default value is set for a 220MHz clock. This value can be reconfigured using the following equation: ceiling(46ns / efuse_clk period) where efuse_clk is selected by the CFG register. |