tsu_timer_incr (GEM) Register Description
| Register Name | tsu_timer_incr |
|---|---|
| Offset Address | 0x00000001DC |
| Absolute Address |
0x00FF0B01DC (GEM0) 0x00FF0C01DC (GEM1) 0x00FF0D01DC (GEM2) 0x00FF0E01DC (GEM3) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | 1588 Timer Increment Register |
tsu_timer_incr (GEM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:24 | roRead-only | 0x0 | Reserved, read as 0, ignored on write. |
| num_incs | 23:16 | rwNormal read/write | 0x0 | Number of incs before alt inc. The number of increments after which the alternative increment is used. |
| alt_ns_incr | 15:8 | rwNormal read/write | 0x0 | Alternative nanoseconds count. Alternative count of nanoseconds by which the 1588 timer nanoseconds register will be incremented each clock cycle. |
| ns_increment | 7:0 | rwNormal read/write | 0x0 | A count of nanoseconds by which the 1588 timer nanoseconds register will be incremented each clock cycle. These are the most significant 8 bits of the 32 bit timer_increment counter. The tsu_timer_incr_sub_nsec register holds the least significant 24 bits of the increment. |