tsu_timer_incr_sub_nsec (GEM) Register Description
| Register Name | tsu_timer_incr_sub_nsec |
|---|---|
| Offset Address | 0x00000001BC |
| Absolute Address |
0x00FF0B01BC (GEM0) 0x00FF0C01BC (GEM1) 0x00FF0D01BC (GEM2) 0x00FF0E01BC (GEM3) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | 1588 Timer Increment Register sub nsec |
tsu_timer_incr_sub_nsec (GEM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| sub_ns_incr_lsb | 31:24 | rwNormal read/write | 0x0 | These are the least significant bits [7:0] of the sub-ns value by which the 1588 timer will be incremented each clock cycle. |
| Reserved | 23:16 | roRead-only | 0x0 | Reserved, read as 0, ignored on write. |
| sub_ns_incr | 15:0 | rwNormal read/write | 0x0 | These are the most significant bits [23:8] of the sub-ns value by which the 1588 timer will be incremented each clock cycle. 24 bits of sub nanosecond precision gives resolution of approximately 5.86E-17 seconds (16 bits gives 15.2 femtoseconds). |