tsu_timer_msb_sec (GEM) Register Description
| Register Name | tsu_timer_msb_sec |
|---|---|
| Offset Address | 0x00000001C0 |
| Absolute Address |
0x00FF0B01C0 (GEM0) 0x00FF0C01C0 (GEM1) 0x00FF0D01C0 (GEM2) 0x00FF0E01C0 (GEM3) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | 1588 Timer Seconds Register 47:32 |
tsu_timer_msb_sec (GEM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:16 | roRead-only | 0x0 | Reserved, read as 0, ignored on write. |
| timer | 15:0 | rwNormal read/write | 0x0 | TSU timer value (s). Most significant 16 bits of seconds timer count. The register is writeable. The 48-bit counter increments by one when the 1588 nanoseconds counter counts to one second. It may also be incremented or decremented when the timer adjust register is written (if decremented from zero the 48-bit combined count would roll back to 0xFFFFFFFFFFFF). Note: The value of this register is used only when the lower 32 bit register is written to. This s to ensure a single update of the 48 bit seconds value |