tsu_timer_sec (GEM) Register Description
| Register Name | tsu_timer_sec |
|---|---|
| Offset Address | 0x00000001D0 |
| Absolute Address |
0x00FF0B01D0 (GEM0) 0x00FF0C01D0 (GEM1) 0x00FF0D01D0 (GEM2) 0x00FF0E01D0 (GEM3) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | 1588 Timer Seconds Register 31:0 |
tsu_timer_sec (GEM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| timer | 31:0 | rwNormal read/write | 0x0 | 1588 Timer Seconds Register. TSU timer value (s). Least significant 32 bits of seconds timer count. This register is writeable. The 48-bit counter increments by one when the 1588 nanoseconds counter counts to one second. It may also be incremented or decremented when the timer adjust register is written (if decremented from zero the 48-bit combined count would roll back to 0xFFFFFFFFFFFF). |