tx_pfc_pause (GEM) Register Description
| Register Name | tx_pfc_pause |
|---|---|
| Offset Address | 0x00000000C4 |
| Absolute Address |
0x00FF0B00C4 (GEM0) 0x00FF0C00C4 (GEM1) 0x00FF0D00C4 (GEM2) 0x00FF0E00C4 (GEM3) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Transmit PFC Pause Register |
tx_pfc_pause (GEM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:16 | roRead-only | 0x0 | Reserved, read as 0, ignored on write. |
| vector | 15:8 | rwNormal read/write | 0x0 | Priority Vector Pause Size. If bit 17 of the network control register is written with a one then for each entry equal to zero in the Transmit PFC Pause Register[15:8], the PFC pause frames pause quantum field associated with that entry will be taken from the transmit pause quantum register. For each entry equal to one in the Transmit PFC Pause Register [15:8], the pause quantum associated with that entry will be zero. |
| vector_enable | 7:0 | rwNormal read/write | 0x0 | Priority Vector Enable. If bit 17 of the network control register is written with a one then the priority enable vector of the PFC priority based pause frame will be set equal to the value stored in this register [7:0]. |