wol_register (GEM) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

wol_register (GEM) Register Description

Register Namewol_register
Offset Address0x00000000B8
Absolute Address 0x00FF0B00B8 (GEM0)
0x00FF0C00B8 (GEM1)
0x00FF0D00B8 (GEM2)
0x00FF0E00B8 (GEM3)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionWake on LAN Register

wol_register (GEM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:20roRead-only0x0Reserved - read 0, ignored when written.
wol_mask_319rwNormal read/write0x0Wake on LAN multicast hash event enable. When set multicast hash events will cause the wol output to be asserted.
wol_mask_218rwNormal read/write0x0Wake on LAN specific address register 1 event enable. When set specific address 1 events will cause the wol output to be asserted.
wol_mask_117rwNormal read/write0x0Wake on LAN ARP request event enable. When set ARP request events will cause the wol output to be asserted.
wol_mask_016rwNormal read/write0x0Wake on LAN magic packet event enable. When set magic packet events will cause the wol output to be asserted.
addr15:0rwNormal read/write0x0Wake on LAN ARP request IP address. Written to define the least significant 16 bits of the target IP address that is matched to generate a Wake on LAN event. A value of zero will not generate an event, even if this is matched by the received frame.