PS-GTR transceivers support a maximum transfer rate of 6 Gb/s over each lane.
- To minimize the impedance discontinuity at the SOM connector interface, route the PS-GTR signals using a 90Ω differential impedance.
- Match P and N differential signals to within ±0.5 mils of each other.
- Route PS-GTR signals in internal routing layers as a stripline structure.
- Route PS-GTR signals with a maximum of two via transitions. Ensure adequate ground return vias are placed next to the signal vias to minimize crosstalk.
- Route PS-GTR signals to have a maximum via stub length of less than 50 mils. It is a good design practice to minimize the stub length to avoid reflections.
- PS-GTR differential signals to all other signal spacing should be four times the distance between the signal to the nearest GND plane.
- For design flexibility, no transceiver capacitors are added to the data lanes on the PS-GTR transceivers.
- For more information on proper decoupling and interface standards, see the PCB Guidelines for the PS Interface in the Zynq UltraScale+ MPSoC chapter in the UltraScale Architecture PCB Design User Guide (UG583).