This section outlines the configuration and control signals associated with the Zynq UltraScale+ MPSoC on the SOM.
Power-on Reset (PS_POR_B) Signal
This is the Zynq UltraScale+ MPSoC power-on reset signal. In AMD documentation this signal is also described as PS_POR_B. The PS_POR_B signal is an active-Low signal that must be asserted during the SOM power-up sequence. On the SOM, the PS_POR_B signal is connected to the PS_POR_L SOM240 connector signal.
System Reset (PS_SRST_B) Signal
This system reset is primarily used for debug activities and is functionally equivalent to POR_B except for clearing a subset of PS power-on and error registers. See the Zynq UltraScale+ Device Technical Reference Manual (UG1085) for more information.
BOOT_MODE Signals
The BOOT_MODE pins define the physical device that the Zynq UltraScale+ MPSoC uses to read the boot
firmware. The boot firmware is prepackaged as a boot.bin, which is a consolidated boot firmware binary constructed
using the AMD Bootgen tool outlined in the
Bootgen User Guide (UG1283).
The SOM includes two non-volatile storage devices: QSPI and eMMC. The BOOT_MODE strapping defines the primary boot device. Alternative boot devices can be designed on your carrier card via MIO banks 501 and 502. The BOOT_MODE memory device selection resistor strapping is defined in the Zynq UltraScale+ Device Technical Reference Manual (UG1085).
JTAG Port Interfaces
The JTAG interface uses a serial configuration mode, popular for prototyping and board test. The four-pin JTAG interface consisting of pins TMS, TDO, TDI, and TCK is included for debug purposes and recommended to be accessible through the carrier card, regardless of boot mode selected. For more information, see the JTAG Interface section in Zynq UltraScale+ Device Technical Reference Manual (UG1085).
PS_ERROR_OUT Signal, PS_ERROR_STATUS Commands
PS_ERROR_OUT is asserted when there is an accidental loss of power, a hardware error, or an exception in the PMU. For secure scenarios where device status is disabled from external visibility, there are PMU control registers to mask PS_ERROR_OUT. PS_ERROR_OUT is sourced from a 1.8V power domain. For more information, see the Zynq UltraScale+ Device Technical Reference Manual (UG1085).
PS_ERROR_STATUS indicates a secure lockdown state. Alternatively, it can be used by the PMU firmware to indicate system status. For secure scenarios where device status is disabled from external visibility, there are PMU control registers to mask PS_ERROR_STATUS. PS_ERROR_STATUS is sourced from a 1.8V power domain. For more information, see the Zynq UltraScale+ Device Technical Reference Manual (UG1085).
Power Management Unit (PMU)
The PMU processor of the Zynq UltraScale+ MPSoC has access to a subset of the I/O in bank 501 that should be given special consideration during the implementation of power-down and power control functionality in the SOM and carrier card design. The PMU application can be customized by the carrier card designer. However, the AMD PMU reference implementation uses the following pin mappings:
- MIO31 is a SOM/CC pin that can be mapped to a PMU GPI pin. PMU GPI pin can be used to implement functionality like a HW Requested Shutdown.
- MIO32 is a PMU GPO reserved signal.
- MIO33 is the PMU output signal reserved for PL power control. This SW Controlled Power Down for PL is only available on the K24.
- MIO34 is the PMU output signal reserved for LPD/FPD (PS) power control, this SW Controlled Power Down is implemented for both the K26 and K24 SOMs.
- MIO35 is a SOM/CC pin that can be mapped to a PMU GPO pin. A PMU GPO pin can be used for PMU based functionality, like external POR_B control or external watchdog monitor.