The MPSoC package delay and SOM trace length information are defined by the board-to-board connector pin name and associated MPSoC pin function net name. See the trace delay file for the SOM:
When creating an I/O timing model, you should include the AMD Zynq™ UltraScale+™ MPSoC package and SOM PCB signal delays for all MIO, HDIO, and HPIO related interfaces. As the carrier card designer, you must include the trace length definitions associated with your implementation.
The Vivado device model captures the MPSoC-related timing model information. When designing a carrier card, you need to include the physical trace length of the MPSoC to board-to-board connector on the SOM along with the board-to-board connector to peripheral device on your carrier card.