SOM MIO Design Considerations

The Zynq UltraScale+ MPSoC on the SOM has a set of integrated, built-in interface IPs. These interface IPs are made available to external pins through multiplexed I/O (MIO) selection, which can be selected and customized for a carrier card design. The MIO interface configuration is set as part of the Vivado design project through the Vivado processor configuration wizard (PCW).

The design of the SOM carrier card must give special consideration to the MIO pins to ensure that the desired MIO peripherals are mappable to the physical pins defined by the electrical design of the carrier card. The SOM fixes the mapping of MIO bank 500 for SOM based peripherals and a subset of bank 501 for SOM power management signals. The remaining MIO pins are configurable for flexibility in the carrier card design. The full MIO peripheral IP mapping to physical pin mapping is defined in the MIO Interfaces table in Zynq UltraScale+ Device Technical Reference Manual (UG1085). MIO mapping must comply with the Zynq UltraScale+ MPSoC design constraints and requirements.

MIO Bank 500

The SOM fixed MIO configurations for bank 500 are outlined in the following table. This MIO configuration is defined by the physical SOM design and cannot be modified by carrier-card designers. It defines the MIO configuration for the SOM peripherals: QSPI, TPM SPI, LEDs, eMCC, and I2C configuration bus.

MIO Bank 500 – Extensible I2C Bus

This MIO configuration must be considered fixed and pre-populated in the corresponding SOM Vivado board files. In SOM bank 500, predefined configuration of the PS I2C interface is made available to the carrier card via the I2C_SCK and I2C_SDA signals on the som_240_1 connector. If the carrier card does not need to extend this I2C bus, the carrier card should leave them as no connects. If the carrier card design extends this bus, they need to ensure they do not introduce an address conflict with the I2C devices on the SOM. The I2C devices are defined in the corresponding table of the Kria K26 SOM Data Sheet (DS987) and Kria K24 SOM Data Sheet (DS985).

MIO Bank 501 – PMU MIO Considerations

The Zynq UltraScale+ MPSoC platform management unit (PMU) processor has access to a subset of the MIO in bank 501 that are also available to the clock-capable I/O and should be given special consideration for the implementation of power-down and power control functionality of the SOM and carrier card design. The SOM power management reserved pins MIO32–34 and are identified in green. The K26 SOM only implements MIO34. The K24 SOM implements both MIO33 and MIO34.

There are also two pins related to optional PMU features made available in the SOM PMU reference implementation. They implement an external shutdown request and can control an external platform watchdog function. These MIO501 optional feature pins are shown in orange.

There are two PMU accessible pins that require special consideration in your CC design as they can be directly accessed by the PMU auxiliary processor.

• MIO31: PMU input pin
• MIO35: PMU output pin

These pins can also be mapped to the APU GPIO controllers if not used in any special PMU-based functionality.

MIO Bank 501 – UART

The orange color coding in the following table point out special design consideration pins inclusive of the UART.

MIO Bank 502

MIO bank 502 has no pin reservations relative to the carrier card design, beyond those defined in Zynq UltraScale+ Device Technical Reference Manual (UG1085).