The following figures show two example layouts showing the BGA routing breakout areas of a representative 1.0 mm/0.92 mm/0.80 mm pitch Xilinx® device.
Sample Breakout with One Route between BGA Balls and Vias
Figure 1. Top Layer Breakout (1.0 mm/0.92 mm/0.8 mm), One Route
between BGA Balls
Figure 2. Inner Signal Layer One Breakout (1.0 mm/0.92 mm/0.8 mm),
One Route between Vias
Figure 3. Inner Signal Layer Two Breakout (1.0 mm/0.92 mm/0.8 mm),
One Route between Vias
Figure 4. Inner Signal Layer Three Breakout (1.0 mm/0.92 mm/0.8
mm), One Route between Vias
Figure 5. Inner Signal Layer Five Breakout (1.0 mm/0.92 mm/0.8 mm),
One Route between Vias
Sample Breakout with Two Routes between BGA Balls and Vias
Figure 6. Top Layer Breakout (1.0 mm/0.92 mm/0.8 mm), Two Routes
between BGA Balls
Figure 7. Inner Signal Layer One Breakout (1.0 mm/0.92 mm/0.8 mm),
Two Routes between Vias
Figure 8. Inner Signal Layer Two Breakout (1.0 mm/0.92 mm/0.8 mm),
Two Routes between Vias
