Creating and Packaging Custom IP (UG1118) - 2022.1 English

Document ID: UG1118
Release Date: 2022-06-17
Version: 2022.1 English

Vivado Design Suite User Guide Creating and Packaging Custom IP
Creating and Packaging Custom IP
Introduction
Navigating Content by Design Process
Hardware, IP, and Platform Development
Supported IP Packager Inputs
Outputs from IP Packager
Using the Packager Settings
IP Packaging Basics
Introduction
IP Packager Wizard Options
Top-Level HDL Requirements
Custom Functions in HDL
Inferring Signals
Inferring Clock and Reset Interfaces
Inferring Clock Interfaces
Inferring Differential Clock Interfaces
Inferring AXI Signals
Packaging a Design with Global Include Files
Constraints Requirements
Managing Out-of-Context Constraints
Processing Order of Constraints
Upgrading Custom IP
Editing an Existing Custom IP
Editing Your IP in an Existing Project
Editing Your IP in a New Editing IP Project
Editing a Packaged Block Design
Adding an Example Design to the Packager
Setting a Dependency Expression
Versioning and Revision Control
Archiving your Current Project
Using the Create and Package New IP Wizard
Introduction
Using the Create and Package IP Wizard
Packaging Your Current Project
Packaging a Block Design
Using an ELF File within a Packaged Block Design
Packaging a Specified Directory
Creating a New AXI4 Peripheral
Using XPMs
Packaging IP
Introduction
Identification
Adding or Creating New Categories for Packaged IP
Removing Categories from your IP
Compatibility
Adding a Xilinx Family or Part
Adding a Family or Part Explicitly
Adding a Family or Part Using Regular Expressions
Automatic Family Support
File Groups
Adding or Removing Files to File Groups
Manually Adding Files to File Groups
Manually Removing Files from a File Group
Copying Files from a File Group
Adding a File Group
Using File Groups to Add a Custom Logo to Packaged IP
Customization Parameters
Importing Parameters from Top-Level HDL Files
Adding, Removing, and Editing a Parameter
Adding a Parameter
Removing a Parameter
Editing a Parameter
Ports and Interfaces
Updating Ports from a Top-Level HDL
Importing Ports from a Top-Level HDL
Editing a Port
Removing a Port
Adding or Removing Bus Interfaces
Adding an Existing Bus Interface
Creating a New Bus Interface Definition
Removing a Bus Interface
Auto Inferring an Interface
Auto Inferring a Bus Interface
Auto Inferring a Single Bit Interface
Editing an Existing Interface
Editing the Interface Information
Mapping the Interface Ports
Adding and Removing Interface Parameters
Adding Recommended Parameters
Adding Custom Parameters
Removing Parameters
Addressing and Memory
Identifying an Interface for Address Mapping
Adding an Address Parameter
Adding or Removing an Address Parameter
Customization GUI
Adding Parameters to the Layout
Adding Groups to the Layout
Adding Pages to the Layout
Adding Text to the Layout
Review and Package
Re-Packaging IP
Archiving an IP Project
Archiving an IP Project with Source Files
Creating New Interface Definitions
Introduction
Creating a New Interface Definition
Using the Interface Definition Editor
Adding Logical Ports to the Interface
Adding Logical Ports from a Previously Defined Interface
Editing Logical Ports
Setting Tristate Signaling
Completing the Interface Definition Creation
Re-Editing Interface Definitions
Using a New Interface Definition
Encrypting IP in Vivado
Introduction
Licensing
Scope
IEEE 1735 Trust Model
Access Rights Management
Common Rights
Vendor-Specific Rights
Conditional Rights
Understanding IEEE 1735 Structural Elements
Version and Other Pragmas
Common Block Definition
Common Rights
Vendor-Specific Tool Block Definition
Xilinx Tool Rights
Key Definition and Rights Digest Method
Rights Definition
Conditional Rights Definition
Conditional Rights Qualifiers
Valid Rights Specification for Xilinx
Invalid Rights Specification for Xilinx
Encryption Payload
Understanding How Rights Affect Vivado Tools
RTL Encryption Examples
VHDL Syntax
Verilog Syntax
Encrypting IP with Vivado
Syntax:
Xilinx IEEE-1735-2014 Public Key
Third-Party Public Keys
Encrypting a Checkpoint with Vivado
Syntax
Examples
Impact on QoR
Best Practices
Known Limitations
Standard and Advanced File Groups
Introduction
Standard File Groups
Advanced File Groups
Additional Resources and Legal Notices
Xilinx Resources
Solution Centers
Documentation Navigator and Design Hubs
References
Xilinx Web Sites
Vivado Design Suite Documentation
Xilinx IP Documentation
Third-Party Documentation
Xilinx QuickTake Videos
Revision History
Please Read: Important Legal Notices

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