The Vivado Design Suite provides a Tcl command,
encrypt, that performs encryption on IEEE-1735-2014 V2 valid
Verilog, SystemVerilog, and VHDL source files.
encrypt command can also be used on the Verilog or VHDL output from
any stage of the Vivado tool flow.
The RTL source code can be encrypted, and any output files by the
write_vhdl commands later in the tool flow also have the protected IP