When selected, this option uses the sources within the specified folder as the HDL sources for creating the new IP Definition. After the wizard completes, it packages the content of the specified folder as an IP for inclusion in the IP repository.
When packaging a specified directory, the custom IP is packaged through an edit IP project. The default options create an edit IP project in the project temporary location. The edit IP project can be saved for future editing, but a new edit IP project can always be created later.
Use the Package as a library core option for IP libraries that are not to be used as a standalone IP. Instead, these libraries are needed to package a main IP. Once you determine all the needed files, you can package them as library cores (or sub-cores), add them to the IP catalog, and use them to package the main IP.
Use Case and BenefitWith this option, IP packager does not need to look at file structure within a Vivado project to package an IP. Instead, IP packager infers the file types (For Example, synthesis/simulation/etc.) required for packaging from the content and structure of the specified directory. It is advised that for the best result, the specified directory contain a proper folder structure for different types of IP sources as described in the table in Packaging a Specified Directory.
IP Packager Output Rules and Limitations
- Packaging output loses addressing information. Top level module that instantiates the IP cannot modify its addressing.
- Parameter Propagation
- Packager output does not provide access to parameter propagation. However, IP packager can be guided by pragmas.
- ELF Association
- IP packager does not support associated ELF files for simulation. It supports ELF files associated with synthesis.
- The IP packager also does not provide usage of the following capabilities: TTcl/XIT, hierarchical IP, creation of dynamic HLS IP, visibility into HW flows.
- IP Packager
- IP Packager does not currently support packaging System Verilog sources. The currently supported flow is to wrap in a Verilog top before packaging.