The scope of IP encryption and protection in the Vivado Design Suite
tool flow is limited up to the point of bitstream generation. Protection of the
bitstream itself requires encryption of the bitstream on the programmed AMD device, a step that usually resides in the hands of the IP user,
not the IP creator. See
Vivado Design Suite User Guide:
Programming and Debugging (UG908) for more information on
bitstream encryption and the
Although there are many different formats of design source files, IEEE-1735-2014 only applies to Verilog, SystemVerilog, and VHDL formats. These RTL standards are also governed by the IEEE, and it is by mutual agreement that those standards allow IEEE-1735 to define behavior in IP security until such a time as the recommendations in IEEE 1735 can be retrofitted into the original language standards contained in the language reference manuals (LRMs). Popular netlist formats, like EDIF, are not covered by IEEE 1735.