The tutorial design includes timing constraints defined in an XDC file (uart_top.xdc). These constraints were defined for the UART design as a standalone design. However, when packaged as an IP, the design inherits some of the needed constraints from the parent design. In this case, you must modify the XDC file to separate constraints the IP requires when used in the context of a parent design, and the constraints the IP requires when used out-of-context (OOC) in a standalone capacity. This requires splitting the current XDC file. You should prepare the design constraints prior to packaging the design for inclusion in the IP catalog; however, you can also perform these steps after packaging the IP.
To ensure that the packaged IP functions properly in the default OOC design flow, the IP packaging must include a standalone XDC file to define all external clocking information for the IP.
Vivado synthesis uses the standalone XDC file in the OOC synthesis run to constrain the IP to the recommended clock frequency.
When used in the context of a top-level design, the parent XDC file provides the clock constraints and the standalone OOC XDC file is not needed.
For more information on the OOC design flow, and the use of the DCP file, see the Vivado Design Suite User Guide: Designing with IP (UG896).