- Platform name
- xilinx_u200_gen3x16_xdma_base_2
- Supported by
- Vitis tools 2021.1 through 2022.1, with support planned through 2022
- Platform UUID
-
0dd37306b7f657a3bd57680fe9dad3a1 - Interface UUID
-
0b095b81fa2be6bd452472b1c1474f18 - Release Date
- April 2022
- Created by
- 2021.1 tools
- Supported XRT versions
- 2021.1 through 2022.1, with support planned through 2022
- Satellite controller (SC) FW release
- Initial release 4.6.11
- Link speed
- PCIe Gen3 x16
- Target cards
-
- A-U200-A64G-PQ-G
- A-U200-P64G-PQ-G
For more information, see Alveo U200 Data Center Accelerator Card.
- Release Notes
- Change log and known issues for the platform and the SC and CMC firmware are available in the Alveo U200 Master Release Notes Answer Record 75172.
The platform implements the device floorplan shown in the following figure and uses resources across the multiple super logic regions (SLR) of the device. The static and dynamic regions are shown across the FPGA SLRs, along with the available DDR memory connections associated with each SLR.
To get the same information for development platforms, after you
install the Vitis unified software platform,
use the platforminfo command utility. It reports
information on interfaces, clocks, valid SLRs, allocated resources, and memory in a
structured format. For more information, see
platforminfo Utility in the
Application Acceleration Development flow of the Vitis Unified Software Platform Documentation
(UG1416).
Memory
The Alveo U200 card has a total of four available DDR memory banks. All but DDR[1] are located in the dynamic region. In addition, it is possible to use the device logic resources for small, fast, on-chip memory accesses as PLRAM. The following table lists the allocation of memory resources per SLR.
| Resources | SLR 0 | SLR 1 | SLR 2 |
|---|---|---|---|
| DDR memory channels (system port name) | DDR[0] (16 GB DDR4) | DDR[1] (16 GB DDR4, static region) DDR[2] (16 GB DDR4, dynamic area) |
DDR[3] (16 GB DDR4) |
| PLRAM memory channels (system port name) | PLRAM[0] (128K, Block RAM) | PLRAM[1] (128K Block RAM) | PLRAM[2] (128K Block RAM) |
| Host memory channels (system port name) | No connections | No connections | HOST[0] 16 GB on host |
Clocking
The platform provides a 300 MHz default clock to run the accelerator.
Available Resources After Platform Installation
The following table lists the available resources in the dynamic region of each SLR. It represents the total device resources after subtracting those used by the static region.
| Resource | SLR 0 | SLR 1 | SLR 2 |
|---|---|---|---|
| CLB LUT | 388K | 205K | 385K |
| CLB register | 776K | 410K | 770K |
| Block RAM tile | 720 | 420 | 720 |
| UltraRAM | 320 | 160 | 320 |
| DSP | 2280 | 1320 | 2280 |
Deployment Platform Installation
To run applications with this platform, download the deployment installation packages corresponding to your OS listed in the following table. Then, use the installation procedures described in Getting Started with Alveo Data Center Accelerator Cards (UG1301).
| OS | Download Link |
|---|---|
| Ubuntu | https://www.xilinx.com/bin/public/openDownload?filename=xilinx-u200-gen3x16-xdma_2022.1_2022_0415_2123-all.deb.tar.gz |
| Redhat/CentOS | https://www.xilinx.com/bin/public/openDownload?filename=xilinx-u200-gen3x16-xdma_2022.1_2022_0415_2123-noarch.rpm.tar.gz |
Accelerated applications have software dependencies. Work with your accelerated application provider to determine which XRT version to install.
Development Platform Installation
For developing applications for use with the Alveo Data Center accelerator cards you must install and use the Vitis software platform. To set up an accelerator card for use in the development environment, follow the installation steps in:
- Vitis Software Platform Installation in the Vitis Unified Software Platform Documentation (UG1416)
- Installing Xilinx Runtime in the Vitis Unified Software Platform Documentation (UG1416)