U250 Gen3x16 XDMA 4_1 Platform

Alveo Data Center Accelerator Card Platforms User Guide (UG1120)
Document ID
UG1120
Release Date
2023-10-11
Revision
2.0.1 English
Platform name
xilinx_u250_gen3x16_xdma_4_1
Deployment name
xilinx_u250_gen3x16_xdma_4_1_202210_1
Supported by
See Table 1 for supported tools versions
Logic UUID
F8DAC62E-49D9-B0AA-E9FC-6F260D9D0DFB
Interface UUID
807A580E-5F50-7D48-484D-26C2217AA787
Release Date
April 2022
Created by
2022.1 tools
Supported XRT versions
2022.1 with support planned through 2023
Satellite controller (SC) FW release
Initial release 4.6.6

For the latest SC firmware release notes, see the Alveo U200/U250 Satellite Controller Release Notes 75174.

Link speed
Gen3 x16
Target cards
  • A-U250-A64G-PQ-G
  • A-U250-P64G-PQ-G

For more information, see Alveo U250 Data Center Accelerator Card.

Release Notes
Change log and known issues for the platform and the SC and CMC firmware are available in the Alveo U250 Master Release Notes Answer Record 75180.

Platform Details

xilinx_u250_gen3x16_xdma_4_1 is a DFX-2RP two-stage platform, which consists of both a base and shell partition. The platform implements the device floorplan shown in the following figure and uses resources across the multiple super logic regions (SLR) of the device. The static and dynamic regions are shown across the SLRs, along with the available DDR memory connections associated with each SLR.

Figure 1. Floorplan

To get the same information for development platforms, if you install the Vitis unified software platform, use the platforminfo command utility. It reports information on interfaces, clocks, valid SLRs, allocated resources, and memory in a structured format. For more information, see platforminfo Utility in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416).

Note: Prior to running an application on this DFX-2RP platform, it is necessary to first program the shell partition. For more information, see 75975.

Memory

The Alveo U250 card has a total of four available DDR memory banks. In addition, it is possible to use device logic resources for small, fast, on-chip memory accesses as PLRAM. The following table lists the allocation of memory resources per SLR.

Note: For details on assigning kernels to DDR memory channels, see Kernel SLR and DDR Memory Assignments in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416).
Table 1. Available Memory Resources per SLR
Resources SLR 0 SLR 1 SLR 2 SLR3
DDR memory channels (system port name) DDR[0] (16 GB DDR4) DDR[1] (16 GB DDR4) DDR[2] (16 GB DDR4) DDR[3] (16 GB DDR4)
PLRAM memory channels (system port name) PLRAM[0] (128K, Block RAM) PLRAM[1] (128K Block RAM) PLRAM[2] (128K Block RAM) PLRAM[3] (128K Block RAM)
Host memory channels (system port name) No connections No connections HOST[0] 16 GB on host No connections

Clocking

The platform provides a 300 MHz default clock to run the accelerator.

Available Resources After Platform Installation

The following table lists the available resources in the dynamic region of each SLR. It represents the total device resources after subtracting those used by the static region.

Table 2. Platform Resource Availability per SLR
Resource SLR 0 SLR 1 SLR 2 SLR 3
CLB LUT 420K 205K 407K 424K
CLB register 840K 411K 815K 849K
Block RAM tile 668 384 660 672
UltraRAM 312 128 308 320
DSP 3032 1536 2994 3072

Card Thermal and Electrical Protections

The following table lists the power and thermal thresholds for this platform. See CT feature details in Platform Features for how these thresholds are used.

Table 3. Platform Thermal and Electrical Protection Thresholds
Sensor Description Clock Throttling Threshold Clock Shutdown Threshold
12V PEX Current 1 5.5A 5.75A
12v AUX Current 2
  • 6.25A (2x3 PCIe AUX power)
  • 12.5A (2x4 PCIe AUX power)
  • Not measured when PCIe AUX power not connected
  • 6.5A (2x3 PCIe AUX power)
  • 13A (2x4 PCIe AUX power)
  • Not measured when PCIe AUX power not connected
VCCINT Temperature 105°C 110°C
FPGA Temperature 92°C 97°C
  1. 12V PEX Current represents power from the PCIe power rail.
  2. 12V AUX current represents power from the auxiliary power connector.

Deployment Platform Installation

To run applications with this platform, navigate to the (see the Alveo Boards and Kits landing page) tab corresponding to your card and download the deployment installation packages and installation guide. Follow the procedures described in the installation guide to install the deployment platform.

Note: Prior to running an application on DFX-2RP platforms, it is necessary to first program the shell partition. For more information, see 75975.

Accelerated applications have software dependencies. Work with your accelerated application provider to determine which XRT version to install.

Development Platform Installation

For developing applications for use with the Alveo Data Center accelerator cards you must install and use the Vitis software platform. To set up an accelerator card for use in the development environment, follow the installation steps in: