U280 Gen3x16 XDMA base_1 Platform

Alveo Data Center Accelerator Card Platforms User Guide (UG1120)

Document ID
Release Date
1.9 English
Platform name
Supported by
Vitis tools 2022.1.1
Logic UUID
Interface UUID
Release Date
Created by
2022.1.1 tools
Supported XRT versions
2022.1 with support planned through 2023
Satellite controller (SC) FW release

Initial release 4.3.27

Link speed
Gen3 x16
Target cards
  • A-U280-A32G-DEV-G
  • A-U280-P32G-PQ-G

For more information, see Alveo U280 Data Center Accelerator Card.

Release Notes
Change log and known issues for the platform and the SC and CMC firmware are available in the Alveo U280 Master Release Notes Answer Record 75183.

Platform Details

The platform implements the device floorplan shown in the following figure and uses resources across the multiple super logic regions (SLR) of the device. The static and dynamic regions are shown across the SLRs, along with the available DDR memory connections associated with each SLR.

Figure 1. Floorplan

To get the same information for development platforms, if you install the Vitis unified software platform, use the platforminfo command utility. It reports information on interfaces, clocks, valid SLRs, allocated resources, and memory in a structured format. For more information, see platforminfo Utility in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416).


The Alveo U280 card has access to a total of 32 GB DDR memory and 8 GB HBM. The DDR memory banks are accessible through two memory controllers and the HBM is accessible through 32 pseudo channels. In addition, it is possible to use device logic resources for small, fast, on-chip memory accesses as PLRAM. The following table lists the allocation of memory resources per SLR.

Note: For details on assigning kernels to DDR memory channels, see Kernel SLR and DDR Memory Assignments in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416).
Table 1. Available Memory Resources per SLR
Resources SLR 0 SLR 1 SLR 2
DDR memory channels (system port name) DDR[0] (16 GB DDR4) DDR[1] (16 GB DDR4) No resources
HBM memory channels (system port name) HBM[0:31] (8 GB) No resources No resources
PLRAM memory channels (system port name) PLRAM[0:1] (128K, Block RAM) PLRAM[2:3] (128K, Block RAM) PLRAM[4:5] (128K, Block RAM)


The platform provides a 300 MHz default clock to run the accelerator.

Available Resources After Platform Installation

The following table lists the available resources in the dynamic region of each SLR. It represents the total device resources after subtracting those used by the static region.

Table 2. xilinx_u280_gen3x16_xdma_base_1 Platform Resource Availability per SLR
Resource SLR 0 SLR 1 SLR 2
CLB LUT 386K 364K 381K
CLB register 773K 729K 763K
BRAM36 600 576 600
URAM 320 320 320
DSP 2664 2784 2856

Deployment Platform Installation

To run applications with this platform, download the deployment installation packages corresponding to your OS listed in the following table. Then, use the installation procedures described in Getting Started with Alveo Data Center Accelerator Cards (UG1301).

Accelerated applications have software dependencies. Work with your accelerated application provider to determine which XRT version to install.

Development Platform Installation

For developing applications for use with the Alveo Data Center accelerator cards you must install and use the Vitis software platform. To set up an accelerator card for use in the development environment, follow the installation steps in: