U280 Gen3x16 XDMA base_1 Platform

Alveo Data Center Accelerator Card Platforms User Guide (UG1120)
Document ID
UG1120
Release Date
2023-10-11
Revision
2.0.1 English
Platform name
xilinx_u280_gen3x16_xdma_base_1
Deployment name
xilinx_u280_gen3x16_xdma_1_202211_1
Supported by
See Table 1 for supported tool versions
Logic UUID
283BAB8F-654D-8674-968F-4DA57F7FA5D7
Interface UUID
FB2B2C5A-19ED-6359-3FEA-95F51FBC8EB9
Release Date
Created by
2022.1.1 tools
Supported XRT versions
2022.1 with support planned through 2023
Satellite controller (SC) FW release
Initial release 4.3.27

For the latest SC firmware release notes, see the Alveo U280 Satellite Controller Release Notes 75185.

Link speed
Gen3 x16
Target cards
  • A-U280-A32G-DEV-G
  • A-U280-P32G-PQ-G

For more information, see Alveo U280 Data Center Accelerator Card.

Release Notes
Change log and known issues for the platform and the SC and CMC firmware are available in the Alveo U280 Master Release Notes Answer Record 75183.

Platform Details

The platform implements the device floorplan shown in the following figure and uses resources across the multiple super logic regions (SLR) of the device. The static and dynamic regions are shown across the SLRs, along with the available DDR memory connections associated with each SLR.

Figure 1. Floorplan

To get the same information for development platforms, if you install the Vitis unified software platform, use the platforminfo command utility. It reports information on interfaces, clocks, valid SLRs, allocated resources, and memory in a structured format. For more information, see platforminfo Utility in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416).

Memory

The Alveo U280 card has access to a total of 32 GB DDR memory and 8 GB HBM. The DDR memory banks are accessible through two memory controllers and the HBM is accessible through 32 pseudo channels. In addition, it is possible to use device logic resources for small, fast, on-chip memory accesses as PLRAM. The following table lists the allocation of memory resources per SLR.

Note: For details on assigning kernels to DDR memory channels, see Kernel SLR and DDR Memory Assignments in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416).
Table 1. Available Memory Resources per SLR
Resources SLR 0 SLR 1 SLR 2
DDR memory channels (system port name) DDR[0] (16 GB DDR4) DDR[1] (16 GB DDR4) No resources
HBM memory channels (system port name) HBM[0:31] (8 GB) No resources No resources
PLRAM memory channels (system port name) PLRAM[0:1] (128K, Block RAM) PLRAM[2:3] (128K, Block RAM) PLRAM[4:5] (128K, Block RAM)

Clocking

The platform provides a 300 MHz default clock to run the accelerator.

Available Resources After Platform Installation

The following table lists the available resources in the dynamic region of each SLR. It represents the total device resources after subtracting those used by the static region.

Table 2. Platform Resource Availability per SLR
Resource SLR 0 SLR 1 SLR 2
CLB LUT 386K 364K 381K
CLB register 773K 729K 763K
BRAM36 600 576 600
URAM 320 320 320
DSP 2664 2784 2856

Card Thermal and Electrical Protections

The following table lists the power and thermal thresholds for this platform. See CT feature details in Platform Features for how these thresholds are used.

Table 3. Platform Thermal and Electrical Protection Thresholds
Sensor Description Clock Throttling Threshold Clock Shutdown Threshold
12V PEX Current 1 5.5A 5.75A
12v AUX Current 2
  • 6.25A (2x3 PCIe AUX power)
  • 12.5A (2x4 PCIe AUX power)
  • Not measured when PCIe AUX power not connected
  • 6.5A (2x3 PCIe AUX power)
  • 13A (2x4 PCIe AUX power)
  • Not measured when PCIe AUX power not connected
VCCINT Temperature 105°C 110°C
FPGA Temperature 92°C 97°C
  1. 12V PEX Current represents power from the PCIe power rail.
  2. 12V AUX current represents power from the auxiliary power connector.

Deployment Platform Installation

To run applications with this platform, navigate to the Getting Started tab corresponding to your card (see the Alveo Boards and Kits landing page) and download the deployment installation packages and installation guide. Follow the procedures described in the installation guide to install the deployment platform.

Accelerated applications have software dependencies. Work with your accelerated application provider to determine which XRT version to install.

Development Platform Installation

For developing applications for use with the Alveo Data Center accelerator cards you must install and use the Vitis software platform. To set up an accelerator card for use in the development environment, follow the installation steps in: