PCI Express - 2023.2 English

Zynq UltraScale+ MPSoC Software Developer Guide (UG1137)

Document ID
UG1137
Release Date
2023-11-28
Version
2023.2 English

The Zynq UltraScale+ MPSoC provides a controller for the integrated block for PCI® Express v2.1 compliant, AXI-PCIe Bridge, and DMA modules. The AXI-PCIe Bridge provides high-performance bridging between PCIe and AXI.

The following flow diagrams illustrate an example for configuring PCIe root complex for a data transfer.

Figure 1. Example PCIe Flow: Enable the Legacy Interrupts and Create PCIe Root Bus
Figure 2. Example PCIe Flow: Enable the Legacy Interrupts and Create PCIe Root Bus
Figure 3. Example PCIe Flow: Enable MSI Interrupts and Wait for Interrupts
Note: For endpoint operation, refer to the “Controller for PCI Express” section in the Zynq UltraScale+ Device Technical Reference Manual (UG1085).

After the memory space for PCIe bridge and ECAM is mapped, ECAM is enabled for ECAM translations. You then acquire the bus range to set up the bus numbers, and write the primary, secondary, and subordinate bus numbers. The interrupt system must be set up by enabling all the miscellaneous and legacy interrupts. You can parse the ranges property of a PCI host bridge device node, and setup the resource mapping based on its content.

To create a root bus, allocate the PCIe root bus and add initial resources to the bus. If the MSI bit is set, you must enable the message signaling interrupt (MSI). After configuring the MSI interrupts, scan the PCIe slot and enumerate the entire PCIe bus and allocate bus resources to scanned buses. Now, you can add PCIe devices to the system.

For more information on PCI Express, see the “DMA Controller” and the “Controller for PCI Express” sections in the Zynq UltraScale+ Device Technical Reference Manual (UG1085).