FLVA1924

Device Reliability Report (UG116)

Document ID
UG116
Release Date
2023-05-17
Revision
10.17 English
Table 1. Package Details (All Dimensions in mm)
Package Size I/O Pitch Ball/ Column Size Pad Opening Pad Type Die Size Substrate
FLVA1924 45 x 45 1924 1.00 0.60 0.53 SMD

14.4 x 23 x 0.10 (2 pcs)

25 x 31 x 0.50

2.00 thick, 18-layer

Mother Board Design and Assembly Details

  • 28-layer, Megtron-6, 290 x 140 x 3.4 mm size, OSP finish
  • 0.53 mm pad diameter/0.63 mm solder mask opening (NSMD pads)
  • Board layer structure: 28 layer with simulated power, ground (70% metal), and signal (40% metal) layer
  • 0.127 mm laser cut stencil, 0.530 mm aperture, Indium 8.9HF paste

Test Condition

  • 0°C–100°C, 40-minute thermal cycle, 10-minute dwells, 10°C/minute ramp rate

Failure Criteria

  • Continuous scanning of daisy chain nets with event detector
  • FAIL: Resistance of net > threshold resistance (500Ω), 10 events (maximum), 1 μs duration (maximum)
Table 2. Summary of Test Results
Package Cycles Completed Number Tested Number Failed First Failure (Cycle) Characteristic Life (Cycle)
FLVA1924 4605 32 25 2759 4222

Weibull Plots

Figure 1. Cycles to Failure in the Second-Level Reliability Tests for FLVA1924