The HAST test is conducted under the conditions of 130°C, 85% RH and VDD bias or 110°C, 85% RH and VDD bias. Package preconditioning is performed on the testing samples
prior to the HAST test.
Summary
Table 1. Summary of High Accelerated Stress Test Results
| Device |
Stress Condition |
Lot Quantity |
Fail Quantity |
Device Quantity |
Total Device Cycles |
| XC3SxxxA |
110°C / 85%RH |
2 |
0 |
90 |
47,520 |
| XC6Sxxx |
110°C / 85%RH |
4 |
0 |
180 |
71,280 |
| 7 series FPGAs and Zynq-7000 SoCs |
110°C / 85%RH |
11 |
0 |
488 |
257,664 |
Data
Table 2. Summary of HAST Test Results XC3SxxxA
| Device |
Stress Condition |
Lot Quantity |
Fail Quantity |
Device Quantity |
Total Device Cycles |
| XC3S200A |
110°C / 85%RH |
2 |
0
|
90 |
47,520 |
| XC3SxxxA |
110°C / 85%RH |
2 |
0
|
90 |
47,520 |
Table 3. Summary of HAST Test Results XC6Sxxx
| Device |
Stress Condition |
Lot Quantity |
Fail Quantity |
Device Quantity |
Total Device Cycles |
| XC6SLX45 |
110°C / 85%RH |
4 |
0
|
180 |
71,280 |
| XC6Sxxx |
110°C / 85%RH |
4 |
0
|
180 |
71,280 |
Table 4. Summary of HAST Test Results 7 series FPGAs and Zynq-7000 SoCs
| Device |
Stress Condition |
Lot Quantity |
Fail Quantity |
Device Quantity |
Total Device Cycles |
| XC7A35T |
110°C / 85%RH |
4 |
0
|
179 |
94,512 |
| XC7Z020 |
110°C / 85%RH |
7 |
0
|
309 |
163,152 |
| 7 series FPGAs and Zynq-7000 SoCs |
110°C / 85%RH |
11 |
0
|
488 |
257,664 |