Temperature Cycling Test

Device Reliability Report (UG116)
Document ID
UG116
Release Date
2023-05-17
Revision
10.17 English

The temperature cycling test is conducted under the conditions of predefined maximum and minimum temperatures and in air-to-air environment. Package precondition is performed on the testing samples prior to the temperature cycling test.

Summary

Table 1. Summary of Temperature Cycling Test Results
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC3Sxxx TCB 2 0 80 120,000
XC3SxxxA TCB 2 0 80 120,000
XC3SxxxE TCB 12 0 474 788,500
XC5VxXxxx TCB 4 0 180 270,000
XC6Sxxx TCB 4 0 160 320,000
XC6VxXxxx TCB 4 0 179 268,500
7 series FPGAs and Zynq-7000 SoCs TCB 13 0 522 925,000
UltraScale devices TCB 14 0 627 918,000
UltraScale+ devices TCB, TCG 27 0 1158 1,848,500
Versal devices TCB 29 0 625 698,100

Data

Table 2. Summary of Temperature Cycling Test Results XC3Sxxx
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC3S1000 TCB 2 0 80 120,000
XC3Sxxx TCB 2 0 80 120,000
Table 3. Summary of Temperature Cycling Test Results XC3SxxxA
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC3S200A TCB 2 0 80 120,000
XC3SxxxA TCB 2 0 80 120,000
Table 4. Summary of Temperature Cycling Test Results XC3SxxxE
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC3S1200E TCB 4 0 155 310,000
XC3S250E TCB 4 0 160 240,000
XC3S500E TCB 4 0 159 238,500
XC3SxxxE TCB 12 0 474 788,500
Table 5. Summary of Temperature Cycling Test Results XC5VxXxxx
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC5VLX110T TCB 4 0 180 270,000
XC5VxXxxx TCB 4 0 180 270,000
Table 6. Summary of Temperature Cycling Test Results XC6Sxxx
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC6SLX45 TCB 4 0 160 320,000
XC6Sxxx TCB 4 0 160 320,000
Table 7. Summary of Temperature Cycling Test Results XC6VxXxxx
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC6VLX240T TCB 4 0 179 268,500
XC6VxXxxx TCB 4 0 179 268,500
Table 8. Summary of Temperature Cycling Test Results 7 series FPGAs and Zynq-7000 SoCs
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC7A100T TCB 4 0 158 237,000
XC7S50 TCB 2 0 80 120,000
XC7Z020 TCB 7 0 284 568,000
7 series FPGAs and Zynq-7000 SoCs TCB 13 0 522 925,000
Table 9. Summary of Temperature Cycling Test Results UltraScale devices
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XCKU025 TCB 1 0 45 67,500
XCKU040 TCB 5 0 224 336,000
XCKU060 TCB 2 0 90 135,000
XCVU095 TCB 6 0 268 379,500
UltraScale devices TCB 14 0 627 918,000
Table 10. Summary of Temperature Cycling Test Results UltraScale+ devices
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XCKU15P TCB 1 0 45 67,500
XCVU13P TCG 8 0 351 481,500
XCVU37P TCG 1 0 25 37,500
XCZU15EG TCB 3 0 127 190,500
XCZU27DR TCB 1 0 44 66,000
XCZU3EG TCB 9 0 388 761,000
XCZU9EG TCB 4 0 178 244,500
UltraScale+ devices TCB, TCG 27 0 1158 1,848,500
Table 11. Summary of Temperature Cycling Test Results Versal devices
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XCVC1702 TCB 6 0 96 96,000
XCVC1902 TCB 4 0 172 245,100
XCVM1802 TCB 3 0 75 75,000
XCVM1402 TCB 10 0 140 140,000
XCVP1202 TCB 6 0 142 142,000
Versal devices TCB 29 0 625 698,100