Temperature Humidity with Bias Test

Device Reliability Report (UG116)
Document ID
UG116
Release Date
2023-05-17
Revision
10.17 English

The THB test is conducted under the conditions of 85°C and 85% RH and VDD bias. Package preconditioning is performed on the testing samples prior to the THB test.

The failures listed in the following table are also listed by device with failure analysis results in the footnotes.

Summary

Table 1. THB Test Results for Si Gate CMOS Devices
Device Lot Quantity Fail Quantity Device Quantity Total Device Hours
XC3Sxxx 4 0 180 225,000
XC3SxxxE 12 0 531 885,000
XC5VxXxxx 4 0 181 249,000
XC6VxXxxx 4 0 179 268,500
7 series FPGAs and Zynq-7000 SoCs 2 0 90 112,500
UltraScale devices 11 0 491 714,000
UltraScale+ devices 15 0 662 1,145,500
Versal devices 4 0 179 268,500

Data

Table 2. THB Test Results for Si Gate CMOS Devices XC3Sxxx
Device Lot Quantity Fail Quantity Device Quantity Total Device Hours
XC3S1000 1 0 45 45,000
XC3S400 3 0 135 180,000
XC3Sxxx 4 0 180 225,000
Table 3. THB Test Results for Si Gate CMOS Devices XC3SxxxE
Device Lot Quantity Fail Quantity Device Quantity Total Device Hours
XC3S100E 1 0 45 67,500
XC3S1200E 4 0 177 354,000
XC3S250E 3 0 130 195,000
XC3S500E 4 0 179 268,500
XC3SxxxE 12 0 531 885,000
Table 4. THB Test Results for Si Gate CMOS Devices XC5VxXxxx
Device Lot Quantity Fail Quantity Device Quantity Total Device Hours
XC5VLX110T 4 0 181 249,000
XC5VxXxxx 4 0 181 249,000
Table 5. THB Test Results for Si Gate CMOS Devices XC6VxXxxx
Device Lot Quantity Fail Quantity Device Quantity Total Device Hours
XC6VHX380T 1 0 45 67,500
XC6VLX240T 3 0 134 201,000
XC6VxXxxx 4 0 179 268,500
Table 6. THB Test Results for Si Gate CMOS Devices 7 series FPGAs and Zynq-7000 SoCs
Device Lot Quantity Fail Quantity Device Quantity Total Device Hours
XC7S50 2 0 90 112,500
7 series FPGAs and Zynq-7000 SoCs 2 0 90 112,500
Table 7. THB Test Results for Si Gate CMOS Devices UltraScale devices
Device Lot Quantity Fail Quantity Device Quantity Total Device Hours
XCKU025 1 0 45 67,500
XCKU040 4 0 176 241,500
XCKU060 1 0 45 67,500
XCKU115 5 0 225 337,500
UltraScale devices 11 0 491 714,000
Table 8. THB Test Results for Si Gate CMOS Devices UltraScale+ devices
Device Lot Quantity Fail Quantity Device Quantity Total Device Hours
XCZU15EG 4 0 180 270,000
XCZU3EG 6 0 261 522,000
XCZU7EV 1 0 44 88,000
XCZU9EG 4 0 177 265,500
UltraScale+ devices 15 0 662 1,145,500
Table 9. THB Test Results for Si Gate CMOS Devices Versal devices
Device Lot Quantity Fail Quantity Device Quantity Total Device Hours
XCVC1902 4 0 179 268,500
Versal devices 4 0 179 268,500