Address Map - 2023.1 English

Zynq UltraScale+ MPSoC ZCU106 Video Codec Unit Targeted Reference Design User Guide (UG1250)

Document ID
UG1250
Release Date
2023-05-16
Version
2023.1 English

Table: Address Map for IP Blocks of the VCU TRD Full-fledged Design shows the address map for various IP blocks used in PL for the VCU TRD full-fledged design.

Table 5-1: Address Map for IP Blocks of the VCU TRD Full-fledged Design

IP Core

Base Address

Offset

AXI Interrupt Controller

0x00A0052000

4K

HDMI I2C Controller

0x00A0050000

4K

MIPI CSI-2 Receiver Subsystem

0x00A00F0000

64K

Sensor I2C Controller

0x00A0051000

4K

Sensor Demosaic

0x00A0250000

64K

HDMI Frame Buffer Read

0x00A0040000

64K

HDMI Frame Buffer Write 0

0x00A0010000

64K

TPG Frame Buffer Write

0x00A00C0000

64K

CSI Frame Buffer Write

0x00A0260000

64K

HDMI Frame Buffer Write 1

0x00A02B0000

64K

HDMI Frame Buffer Write 2

0x00A02C0000

64K

HDMI Frame Buffer Write 3

0x00A0280000

64K

HDMI Frame Buffer Write 4

0x00A0290000

64K

HDMI Frame Buffer Write 5

0x00A02A0000

64K

HDMI Frame Buffer Write 6

0x00A02D0000

64K

Gamma LUT

0x00A0270000

64K

HDMI 1.4/2.0 Receiver Subsystem v2.0

0x00A0000000

64K

HDMI 1.4/2.0 Transmitter Subsystem v2.0

0x00A0020000

128K

Video Mixer

0x00A0070000

64K

Video Processing Subsystem (VPSS)

0x00A0080000

256K

Video Processing Subsystem (VPSS-CSC)

0x00A0240000

64K

Video Processing Subsystem (VPSS-Scaler)

0x00A0200000

256K

Video Timing Controller

0x00A00D0000

64K

Video Test Pattern Generator (TPG)

0x00A00E0000

64K

H.264/H.265 Video Codec Unit (VCU)

0x00A0100000

1M

Video PHY Controller

0x00A0060000

64K

Video Scene Change

0x00A02E0000

64K

Table: Address Map for Audio Design IP Blocks shows the address map of various IP blocks used in the PL of an audio design.

Table 5-2: Address Map for Audio Design IP Blocks

IP Core

Base Address

Offset

Audio Clock Recovery

0x00_A029_0000

64K

Audio Formatter1

0x00_A005_2000

4K

Audio Formatter2

0x00_A005_1000

4K

AXI GPIO

0x00_A005_3000

4K

AXI Interrupt Controller

0x00_A005_5000

4K

HDMI ACR Control

0x00_A005_6000

4K

S_AXI

0x00_A005_0000

4K

I2S Receiver

0x00_A00C_0000

64K

I2S Transmitter

0x00_A00D_0000

64K

MIPI CSI-2 Receiver Subsystem

0x00_A00F_0000

64K

Sensor I2C Controller

0x00_A005_4000

4K

Sensor Demosaic

0x00_A025_0000

64K

HDMI Frame Buffer Read

0x00_A004_0000

64K

HDMI Frame Buffer Write

0x00_A001_0000

64K

MIPI Frame Buffer Write

0x00_A026_0000

64K

Gamma LUT

0x00_A027_0000

64K

HDMI Receiver Subsystem

0x00_A000_0000

64K

HDMI Transmitter Subsystem

0x00_A002_0000

128K

Video Mixer

0x00_A007_0000

64K

Video Processing Subsystem (VPSS)

0x00_A008_0000

256K

Video Processing Subsystem (VPSS-CSC)

0x00_A024_0000

64K

Video Processing Subsystem (VPSS-Scaler)

0x00_A020_0000

256K

Scene Change

0x00_A028_0000

64K

H.264/H.265 Video Codec Unit (VCU)

0x00_A010_0000

1M

Video PHY Controller

0x00_A006_0000

64K

Table: Address Map for PLDDR SDI Design IP Blocks shows the address map of various IP blocks used in the PL of an SDI design.

Table 5-3: Address Ma p for PLDDR SDI Design IP Blocks

IP Core

Base Address

Offset

Audio Formatter

0x00_A000_0000

4K

AXI GPIO

0x00_A006_0000

4K

GPIO Resets

0x00_A006_3000

4K

GPIO Registers

0x00_A006_1000

4K

GPIO Registers

0x00_A006_2000

4K

SDI TX Frame Buffer Read

0x00_B001_0000

64K

Video frame Buffer Read

0x00_A00C_0000

64K

SDI RX Frame Buffer Write

0x00_B000_0000

64K

Video frame Buffer Write

0x00_A00D_0000

64K

SDI Receiver Subsystem

0x00_A003_0000

64K

SDI Transmitter Subsystem

0x00_A004_0000

128K

SDI Audio Embed

0x00_A001_0000

64K

SDI Audio Extract

0x00_A002_0000

64K

H.264/H.265 Video Codec Unit (VCU)

0x00_A010_0000

1M

VCU DDR4 Controller

0x48_0000_0000

2G

Table: Address Map for HDMI HDR10 PLDDR Design IP Blocks shows the address map of various IP blocks used in the PL of an HDMI DDR design.

Table 5-4: Address Map for HDMI HDR10 PLDDR Design IP Blocks

IP Core

Base Address

Offset

HDMI Frame Buffer Write 0

0x00_A001_0000

64K

Input Key Management Block

0x00_A008_0000

64K

Output Key Management Block

0x00_A009_0000

64K

AXI Interrupt Controller

0x00_A00A_0000

64K

HDMI Receiver Subsystem

0x00_A040_0000

512K

Video Processing Subsystem (VPSS)

0x00_A004_0000

256K

HDMI Frame Buffer Read

0x00_A00B_0000

64K

HDMI Transmitter Subsystem

0x00_A030_0000

512K

Video Mixer

0x00_A00C_0000

64K

AXI IIC Bus Interface

0x00_A00D_0000

4K

Video Frame Buffer Read

0x00_A011_0000

64K

Video Frame Buffer Write

0x00_A012_0000

64K

H.264/H.265 Video Codec Unit (VCU)

0x00_A020_0000

1M

VCU DDR4 Controller

0x48_0000_0000

2G

Video PHY Controller

0x00_A013_0000

64K

Table: Address Map for LLP2 Audio NV12 Blocks shows the address map of various IP blocks used in the PL of an HDMI DDR design.

Table 5-5: Address Map for LLP2 Audio NV12 Blocks

IP Core

Base Address

Offset

Audio Clock Recovery

0x00_A029_0000

64K

Audio Formatter1

0x00_A005_2000

4K

Audio Formatter2

0x00_A005_1000

4K

AXI GPIO

0x00_A005_3000

4K

Audio Clock Wizard

0x00_A00E_0000

64K

AXI Interrupt Controller

0x00_A005_5000

4K

HDMI ACR Control

0x00_A005_6000

4K

HDMI Frame Buffer Write

0x00_A001_0000

64K

HDMI Frame Buffer Write

0x00_A028_0000

64K

HDMI Frame Buffer Write

0x00_A02A_0000

64K

HDMI Frame Buffer Write

0x00_A02B_0000

64K

HDMI Receiver subsystem

0x00_A000_0000

64K

Video Processing Subsystem (VPSS)

0x00_A008_0000

256K

HDMI Frame Buffer Read

0x00_A004_0000

64K

HDMI Transmitter Subsystem

0x00_A002_0000

128K

Video Mixer

0x00_A007_0000

64K

Sync IP

0x00_A02C_0000

64K

Video Processing Subsystem (VPSS-CSC)

0x00_A024_0000

64K

Video Processing Subsystem (VPSS-Scaler)

0x00_A020_0000

256K

HDMI_ctrl_iic

0x00_A005_0000

4K

H.264/H.265 Video Codec Unit (VCU)

0x00_A010_0000

1M

Video PHY Controller

0x00_A006_0000

64K