Capture/Input Pipelines - 2023.1 English

Zynq UltraScale+ MPSoC ZCU106 Video Codec Unit Targeted Reference Design User Guide (UG1250)

Document ID
UG1250
Release Date
2023-05-16
Version
2023.1 English

The HDMI RX capture pipeline (in the PL) consists of the HDMI RX Subsystem IP, Video Processing Subsystem IP enabled for VPSS and color space conversion functionality, and the Frame Buffer Write IP that converts the packed video data to a semi-planar format and writes the data into memory.

The Test Pattern Generator (TPG) capture pipeline (in the PL) consists of the TPG sourcing the live video input that goes to a Frame Buffer Write IP.

The MIPI CSI-2 RX capture pipeline (FMC + PL) consists of an IMX274 sensor, MIPI CSI-2 Receiver Subsystem (CSI RX), the AXI4-Stream subset converter, Demosaic IP, Gamma LUT IP, Video Processing Subsystem IP enabled for VPSS and color space conversion functionality, and the Frame Buffer Write IP.

The SDI RX capture pipeline (in the PL) consists of the SDI RX Subsystem and Video Processing Subsystem IP enabled for VPSS and color space conversion functionality and the Frame Buffer Write IP.

The audio input/capture pipeline (in the PL) consists of Audio Formatter IP that receives audio input from the HDMI RX Subsystem IP and writes the data to memory.