Clocking - 2022.2 English

Zynq UltraScale+ MPSoC ZCU106 Video Codec Unit Targeted Reference Design User Guide (UG1250)

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2022.2 English

This section describes the clocking mechanism used in the TRD. The primary clock is sourced from si570_user sources that provide a 300 MHz reference clock to the PL. A mixed-mode clock manager (MMCM) block in the PL uses the si570 clock as a primary input clock and generates the reference clock for the VCU PLL and video pixel clock. The VCU PLL generates the core clock and MCU clock based on the input reference. PL_CLK0 from the processing system is also used as the AXI4-Lite clock.

The USER_MGT_SI570_CLOCK is used as source for the DRU_CLK/SDI GT reference clock. This Figure shows the clocking mechanism used for the TRD. The 125 MHz MIG clock is used as the PL DDR ref clock. The VCU_DDR4 soft IP generates the 250 MHz phy_clk required for processing the data.

Note:   The audio design uses pl_clk2 as the Video Pixel clock (instead of MMCM output) for both TX and RX pipelines.

Figure 5-2:      Clocking Mechanism for the TRD

X-Ref Target - Figure 5-2