Display/Output Pipelines - 2023.1 English

Zynq UltraScale+ MPSoC ZCU106 Video Codec Unit Targeted Reference Design User Guide (UG1250)

Document ID
UG1250
Release Date
2023-05-16
Version
2023.1 English

The HDMI TX display pipeline (in the PL) is controlled by the Video Mixer, which fetches both graphics (rendered by GPU in the graphics layer) and the video layer from memory and sends the data to the HDMI TX Subsystem. The HDMI TX Subsystem processes data and sends it out to an external display device.

The DP TX display pipeline (in the PS) consists of the PS DisplayPort controller. DisplayPort direct memory access (DPDMA) fetches both graphics and the video layer from memory. The DisplayPort controller processes data and sends it out to external display devices using the DisplayPort Standard.

The SDI TX display pipeline (in the PL) is controlled by the Video Mixer, which fetches the video layer from memory and sends to the SDI TX Subsystem. The SDI TX Subsystem processes data and sends it out to an external display device.

The USB universal video class (UVC) capture pipeline (in the PS) consists of the USB Controller. It takes recorded video files and writes the data into DDR memory.

The audio output pipeline (in the PL) consists of Audio Formatter IP that reads audio data from memory and sends it out to the HDMI TX Subsystem IP, which sends it to the output device.

The block diagram highlights these two partitions of the design:

The hardware Base Platform consists of all the capture and display pipelines and VCU processing pipelines.