The HDMI TX display pipeline is shown in This Figure.
This pipeline consists of three main components, each of them controlled by the APU via an AXI4-Lite base register interface:
The Video Mixer IP core is configured to support blending of up to two video layers and one graphics layer into one single output video stream. The three layers are configured to be memory-mapped AXI4 interfaces connected to the HP0 high performance PS/PL interface via an AXI interconnect; the main AXI4-Stream layer is unused. The two video layers are configured for 16-bit YUYV, the graphics layer is configured for 32-bit ARGB, (see Video Buffer Format for details). A built-in color space converter and chroma resampler convert the input formats to a 24-bit RGB output format. Pixel-alpha blending is used to blend the graphics layer with the underlying video layers. The AXI4-Stream output interface is a 48-bit bus that transports 2 ppc for up to 2160p60 performance. It is connected to the HDMI TX Subsystem input interface. A GPIO is used to reset the subsystem between resolution changes. For more information refer to the Video Mixer LogiCORE IP Product Guide (PG243) [Ref 15]. To support YUV444 in the HDMI display, this format is enabled in the Frame Buffer Read IP because the Video Mixer IP does not support YUV444 format.
•The HDMI Transmitter Subsystem (HDMI TX) interfaces with PHY layers and provides HDMI encoding functionality. The subsystem is a hierarchical IP that bundles a collection of HDMI TX-related IP sub-cores and outputs them as a single IP. The subsystem generates an HDMI stream from the incoming AXI4-Stream video data and sends the generated TMDS data to the video PHY layer. For more information refer to the HDMI 1.4/2.0 Transmitter Subsystem Product Guide (PG235) [Ref 14].
•The Video PHY Controller is shared between the HDMI RX and HDMI TX pipelines. Refer to HDMI RX Capture Pipeline for more information on the VPHY and its configuration.