LLP2 PL DDR HLG SDI Video Capture and Display - 2022.2 English

Zynq UltraScale+ MPSoC ZCU106 Video Codec Unit Targeted Reference Design User Guide (UG1250)

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2022.2 English

This module enables capture of HLG (high dynamic range)/non-HLG video from an SDI RX subsystem implemented in the PL. It supports the encoding/decoding and transmission of HLG video along with backward-compatible standard dynamic range (SDR) for SDI. The video can be displayed through SDI TX through the PL and recorded in SD cards or USB/SATA drives. The module can stream-in or stream-out encoded data through an Ethernet interface. SDI with dynamic frame rate support is enabled. This module also supports single stream 8-channel audio.

This is the new design approach proposed to use PL_DDR for decoding and PS_DDR for encoding so that DDR bandwidth would be enough to support high-bandwidth VCU applications requiring simultaneous encoder and decoder operations and transcoding at a maximum resolution of 4K @60FPS. This approach makes the most effective use of limited AXI4 read/write issuance capability in minimizing latency for the decoder. DMA buffer sharing requirements determine how capture, display, and intermediate processing stages should be mapped to the PS or PL DDR. PICXO IP is used for synchronization of Tx_out_clk and Rx_out_clk  from the GT. SDI supports fractional and integer frame rates.

This design also support Xilinx's low latency pipeline, in which The VCU encoder and decoder operate in slice mode. An input frame is divided into multiple slices (8 or 16) horizontally. The encoder generates a slice_done interrupt at every end of the slice. Generated NAL unit data can be passed to a downstream element immediately without waiting for the frame_done interrupt. The VCU decoder also starts processing data as soon as one slice of data is ready in its circular buffer instead of waiting for complete frame data. The hardware Sync (syncIP) element is responsible synchronizing buffers between the capture DMA and the VCU encoder, and between the VCU decoder and the display element.

The capture element (FB write DMA) writes video buffers in raster-scan order. SyncIP monitors the buffer level while the capture element is writing into DRAM and allows the encoder to read input buffer data if the requested data is already written by DMA, otherwise it blocks the encoder until DMA completes its writes. On the decoder side, the VCU decoder writes decoded video buffer data into DRAM in block-raster scan order, and displays reads data in raster-scan order. To avoid display under-run problems, software ensures a phase difference of "~frame_period/2", so that the decoder is ahead compared to the display.

Note:   This module supports single-stream for XV20 (YUV 4:2:2 10-bit) pixel format only. This design also supports interlace mode.