• The Video Codec Unit (VCU) processing pipeline (in the PL) consists of the VCU IP which contains the VCU primitive with four 128-bit memory-mapped AXI4 interfaces. The outputs of these interfaces are multiplexed for each of the encoder and decoder ports.
• Sync IP is responsible for synchronizing buffers between Capture DMA and the VCU encoder and is used in LLP2 designs which demand ultra low latency.
• The accelerator processing pipeline (in the PL) consists of a dummy accelerator that has one 128-bit memory-mapped AXI4 interface coming out, which is multiplexed with encoder/decoder ports of the VCU.
Note: The accelerator processing pipeline is only supported for versions up to, and including 2019.1.