Reference Design Overview - 2023.1 English

Zynq UltraScale+ MPSoC ZCU106 Video Codec Unit Targeted Reference Design User Guide (UG1250)

Document ID
UG1250
Release Date
2023-05-16
Version
2023.1 English

The MPSoC has a heterogeneous processor architecture. The TRD makes use of multiple processing units available inside the PS using this software configuration:

The APU consists of quad Arm Cortex-A53 cores configured to run in SMP Linux mode. The main task of the application is to configure and control the video pipelines using a Qt v5.9.4 based graphical user application. See This Figure .

Figure 1-2: Key Reference Design Components

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This Figure shows the software state after the boot process has completed and the individual applications have been started on the target processing units. The TRD does not use virtualization and therefore does not run a hypervisor on the APU.

The APU application controls the following video data paths implemented in the PS and PL (see This Figure ):

Capture pipeline capturing video frames into DDR memory from a high definition media interface (HDMI source connected through the PL, an image sensor on an FMC daughter card connected via MIPI CSI-2 RX Subsystem through the PL, serial digital interface (SDI) source connected through the PL, and a Test Pattern Generator (TPG) implemented inside the PL. Additionally, video can be sourced from a SATA drive, USB 3.0 device, or an SD card, which is also used as a boot device.

Processing (memory-to-memory) pipeline includes VCU encode/decode. Video frames are read from DDR memory, processed by the VCU, and written back to memory.

Display pipeline reading video frames from memory and sending them to a monitor via the DisplayPort TX Controller inside the PS, SDI Transmitter Subsystem through the PL or the HDMI Transmitter Subsystem through the PL. The DisplayPort TX Controller supports two layers—one for video, the other for graphics and the SDI Transmitter Subsystem with mixer IP support up to four layers and HDMI Transmitter Subsystem with mixer IP supports up to eight such layers. The graphics layer is rendered by the GPU.

Audio Capture pipeline to capture audio frames from HDMI-RX, SDI-RX and I2S-RX interfaces.

Audio Renderer pipeline to playback the audio frames through HDMI-TX, SDI-TX, DP, and I2S-TX interfaces.

LLP2 pipeline to stream-out and stream-in live captured video at ultra-low latencies using Sync IP.

The TRD consists of seven designs which are highlighted in different colors as shown in This Figure .

Figure 1-3: VCU TRD Block Diagram

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Note: In This Figure , except for all of the VCU Audio designs , HDMI pipelines in all other designs exclude Audio Formatter IP and thus do not have audio. For XV20 designs PLDDR is included in the processing pipeline.

The remaining blocks are common to all designs. See Targeted Reference Design Details for more details.

The reference design targets the ZCU106 evaluation board. The board has an onboard HDMI transmitter and receiver connector , SDI transmitter and receiver connector, and a DisplayPort connector interface. The evaluation board provides the HDMI reference clock, data recovery unit (DRU) clock, and the reference clock for the design. The PS_REF_CLK is sourced from another dedicated clock generator present on the evaluation board. This Figure shows the block diagram of the TRD along with the board components.

Figure 1-4: High-Level Block Diagram of ZCU106 Device Architecture

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