Reset - 2023.1 English

Zynq UltraScale+ MPSoC ZCU106 Video Codec Unit Targeted Reference Design User Guide (UG1250)

Document ID
UG1250
Release Date
2023-05-16
Version
2023.1 English

A synchronous reset mechanism is used in the TRD. PL_RESET0 is used as a master reset signal. Interconnect and peripheral reset signals are generated using proc_sys_rst IP in the PL.