[This Figure, callout 2, 3, 4, 5]
Four independent single-rank DDR4 interfaces are available on the KCU1500 board, each providing 4 GB of memory and implemented with soldered down DDR4 memory components.
•Part Number: MT40A512M16JY-083E
°8 Gb (512 Mb x 16)
°1.2V 96-ball FBGA
The KCU1500 XCKU115 FPGA DDR interface performance is documented in the Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS892) [Ref 2].
Three of the interfaces (C0, C2, and C3) are 72-bits wide (support for ECC), and the fourth interface (C1) is 64-bits wide (non-ECC). The component memories are configured in a clamshell topology where the devices for a given interface have different chip selects for the top and bottom mounted components.
The memory interface-to-FPGA bank assignments are listed in Table: I/O Bank Voltage Rails. The DDR4 0.6V VTT termination voltages are sourced from four independent TI TPS51200DR regulator circuits.
The KCU1500 DDR4 memory component interfaces adhere to the constraints guidelines documented in the "DDR3/DDR4 Design Guidelines" section of the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150) [Ref 3]. The KCU1500 board DDR4 memory component interfaces are 40Ω impedance implementations. For more details about the Micron DDR4 component memory, see the Micron MT40A512M16JY-083E data sheet at the Micron website [Ref 9].