[This Figure, callout 9]
The system clock source is a Silicon Labs SI5335A quad clock generator/buffer (U47).
•Clock generator: Silicon Labs SI5335A-B06201-GM (CLK0A 300 MHz)
°Frequency plan: FS1, FS0=01
-Input Type: crystal, input frequency 25 MHz
-Device operating mode: clock generator loop bandwidth 1.6 MHz
-CLK0A/0B: 300 MHz 1.8V LVDS
-CLK1A/1B: 156.25 MHz 1.8V LVDS
-CLK2A/2B: 90 MHz 1.8V CMOS (output on A only)
-CLK3A/3B: 33.333 MHz 1.8V CMOS (output on A only)
•Low phase jitter of 0.7pS RMS
Three outputs of the SI5335A U47 are used:
•CLK0A/B
The system clock (SYSCLK) is an LVDS 300 MHz clock wired to SI53340 (U46) 1-to-4 clock buffer, which drives four AC coupled versions of the 300 MHz clock into the clock capable (GC) inputs on the four DDR4 interface banks (C0: bank 45, C1: bank 67, C2: bank 51, and C3: bank 71).
•CLK1A/B
The QSFP0_CLOCK_P/N clock is an AC coupled LVDS 156.25 MHz clock wired to QSFP0 interface MGTH bank 127 MGTREFCLK1P/N input pins AU36 and AU37.
•CLK2A
This 90 MHz single-ended series resistor damped LVCMOS18 FPGA_EMCCLK is wired to FPGA U1 dedicated bank 65 EMCCLK input pin.
•CLK3A is not used.
The system, QSFP0, and EMCCLK clock circuit is shown in This Figure.
