DPAUX (MIO 27-30)

ZCU111 Evaluation Board User Guide (UG1271)

Document ID
UG1271
Release Date
2022-10-06
Revision
1.3 English

[This Figure, callout 29]

The Zynq UltraScale+ RFSoC provides a VESA DisplayPort 1.2 source-only controller that supports up to two lanes of main link data at rates of 1.62 Gb/s, 2.70 Gb/s, or 5.40 Gb/s. The DisplayPort standard defines an auxiliary channel that uses LVDS signaling at a 1 Mb/s data rate, which is translated from single-ended MIO signals to the differential DisplayPort AUX channel, DPAUX (see Table: DPAUX/MIO Connections). The DisplayPort circuit is shown in This Figure.

Table 3-10:      DPAUX/MIO Connections

XCZU28DR (U1) Pin

Net Name

SN74AVC4T245 Level Shifter U10

Pin Name

Pin #

D25

 MIO30_DP_AUX_IN  

 2A1  

8

B25

 MIO29_DP_OE  

 1A2  

7

F25

 MIO28_DP_HPD  

 2A2  

9

C25

 MIO27_DP_AUX_OUT  

 1A1  

6

Figure 3-6:      DisplayPort Circuit

X-Ref Target - Figure 3-6

X20482-displayport.jpg