PMU GPO (MIO 32-37)

ZCU111 Evaluation Board User Guide (UG1271)

Document ID
UG1271
Release Date
2022-10-06
Revision
1.3 English

The platform management unit (PMU) in the Zynq UltraScale+ RFSoC device signals power domain changes using the PMU output pins. The Zynq UltraScale+ RFSoC device PMU GPO pins are connected to inputs of the MSP430 system controller via TXS0108E level-shifter U41. The RFSoC U1 bank 501 and MSP430 U42 pin numbers are listed in Table: XCZU28DR U1 to MSP430 Connections.

Table 3-11:      XCZU28DR U1 to MSP430 Connections

XCZU28DR
(U1) Pin

Net Name

MSP430 U42

Pin Name

Pin #

F26

MIO37_PMU_GPO5

P1_0

13

C27

MIO36_PMU_GPO4

P1_1

14

E26

MIO35_PMU_GPO3

P1_2

15

B27

MIO34_PMU_GPO2

P1_3

16

A27

MIO33_PMU_GPO1

P1_4

17

A26

MIO32_PMU_GPO0

P1_5

18

Through the I2C0 bus RFSoC MIO pins, the PMU has access to the board power controllers and power monitors. See This Figure for more details.

See the Zynq UltraScale+ Device Technical Reference Manual (UG1085) [Ref 3] for more details about the PMU interface.