[This Figure, callout 2]
The PS-side memory is wired to the Zynq UltraScale+ DDRC bank 504 hard memory controller. The PS-side bank 504 memory interface supports 260-pin 64-bit DDR4 SODIMM socket J50. The ZCU111 board is shipped with a DDR4 SODIMM installed:
•Part Number: MTA4ATF51264HZ-2G6E1
°4 GByte 260-pin DDR4 SODIMM
°Single rank x16
°512 Mbit x 64-bit
°Supports 1333 MT/s – 2666 MT/s
The ZCU111 XCZU28DR RFSoC PS DDR interface performance is documented in the Zynq UltraScale+ RFSoC Data Sheet (DS926)[Ref 2].
The ZCU111 DDR4 SODIMM interface adheres to the constraints guidelines documented in the PCB guidelines for DDR4 section of the UltraScale Architecture PCB Design User Guide (UG583) [Ref 4]. The DDR4 SODIMM interface is a 40Ω impedance implementation. Other memory interface details are also available in the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150) [Ref 5]. For more details, see the Micron MTA4ATF51264HZ-2G6E1 data sheet at the Micron website [Ref 15].
The connections between the DDR4 SODIMM socket J50 and XCZU28DR PS bank 504 are referenced in Xilinx Design Constraints.