One PL-side GTY transceiver in bank 128 is provided for the quad SFP28 interface. Available GTY reference clocks include a jitter attenuated recovered clock from a Si5382. SFP+ modules typically provide an I2C based control interface. This I2C interface is accessible for each individual SFP28 module through the I2C multiplexer topology on the ZCU111 board. The RFSoC U1 connections for each quad are referenced in Xilinx Design Constraints.
For additional information on GTY transceivers, see the UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 6].