[This Figure, callout 5]
The ZCU111 board uses a Standard Microsystems Corporation USB3320 USB 2.0 ULPI transceiver at U12 to support a USB connection to the host computer (see This Figure). A USB cable is supplied in the ZCU111 evaluation kit (standard-A connector to host computer, USB 3.0 A connector to ZCU111 board connector J96). The USB3320 is a high-speed USB 2.0 PHY supporting the UTMI+ low pin interface (ULPI) interface standard. The ULPI standard defines the interface between the USB controller IP and the PHY device, which drives the physical USB bus. Using the ULPI standard reduces the interface pin count between the USB controller IP and the PHY device.
The USB3320 is clocked by a 24 MHz crystal (X2). See the Standard Microsystems Corporation (SMSC) USB3320 data sheet for clocking mode details [Ref 16]. The interface to the USB3320 PHY is implemented through the IP in the XCZU28DR RFSoC PS.
Table: USB Jumper Settings describes the jumper settings for the USB 2.0 circuit.
Note: The bold text in Table: USB Jumper Settings identifies the default shunt positions for USB 2.0 high-speed on-the-go (OTG) mode.
Note: The shield for the USB 3.0 micro-B connector (J96) can be tied to GND by a jumper on header J17 pins 2-3 (default). The USB shield can optionally be connected through a series capacitor to GND by installing a capacitor (body size 0402) at location C171 and jumping pins 1-2 on header J17.
The USB3320 ULPI U12 transceiver circuit (see This Figure) has a Micrel MIC2544 high-side programmable current limit switch (U13). This switch has an open-drain output fault flag on pin 2, which turns on LED DS7 if over current or thermal shutdown conditions are detected. DS7 is located in the U13 circuit area (This Figure, callout 53). This Figure shows the ULPI U12 transceiver circuit.
The connections between the USB 2.0 PHY (U12) and the XCZU28DR RFSoC PS bank 502 are referenced in Xilinx Design Constraints.